[RS7-4] A 1.8Gb/s/ch 10mW/ch -23dB Crosstalk Eight-Channel Transimpedance Amplifier Array for LADAR Systems
نویسندگان
چکیده
An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm and consumes 88 μW at 0.4-V supply for 200-MHz operation. Keywords-component; low voltage charge pump, phase locked loop, power efficiency, spur reduction, ultra low voltage
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